Power converter for converting DC power to AC power with adaptive control on characteristics of load

ABSTRACT

A power converter is provided with an inverter unit for converting DC power from a DC power supply into AC power, and a control unit that generates a control signal for controlling the inverter unit. The control unit includes an impedance estimation unit that injects a disturbance signal into a load and derives an estimated value of an impedance of the load based on a voltage signal from the load into which the disturbance signal is injected, the impedance compensator unit whose control parameters are set based on the estimated value of the impedance, and that corrects an output current signal in accordance with the control parameters, a command value unit that outputs a command value indicating a control target value, and a control compensator unit that generates a control signal, based on the command value from the command value unit and the current signal from the impedance compensator unit.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Japanese Patent Application No.2017-239903 filed Dec. 14, 2017, the entire contents of which areincorporated herein by reference.

FIELD

The present invention relates to a power converter for converting DC(direct current) power into AC (alternating current) power andoutputting the AC power.

BACKGROUND

There are power converters that convert DC power generated by a solarcell into AC power. For example, JP 2005-341680A discloses a powercontroller in a system interconnection system that outputs power outputby a DC power supply to a power system. The power controller of JP2005-341680A includes measurement means for measuring the impedance ofthe power system, setting means for setting a control parameter relatingto power that is output to the power system, based on the measuredimpedance, and control means for controlling power that is output to thepower system using the control parameter. As a result of thisconfiguration, an increase in system voltage is reliably and stablysuppressed, and the power generation efficiency and capacity factor areenhanced in the system interconnection system.

JP 2005-341680A is an example of background art.

Generally, a power converter is connected to a system (specifically,pole transformer) via wiring. This wiring has impedance (hereinafter,“system impedance”). In order to perform stable control in a powerconverter interconnected to a system, it is necessary to set controlparameters with consideration for this system impedance. However, thesystem impedance value changes depending on the length of the wiring,and differs according to the environment in which the power converter isinstalled.

When designing power converters, it is difficult to gauge the systemimpedance value of future installation environments beforehand. Thus,heretofore, there were concerns about control becoming unstable inresponse to the system impedance, and power converters were designedwith a margin built into the inductance value of the smoothing inductorfor the AC output voltage with consideration for the maximum impedancevalue that was envisaged. This resulted in increases in the componentsize and the cost of power converters.

SUMMARY

The present invention has been made in view of the above problems, andprovides a power converter that is able to realize favorable control byadapting to characteristics (impedance) of an actual load.

A power converter according to one aspect of the present invention is apower converter for converting DC power from a DC power supply into ACpower and outputting the AC power to a load, the power converterincluding an inverter unit configured to convert DC power from the DCpower supply into AC power, a voltage detection unit configured todetect a voltage of the load and generate a voltage signal, a currentdetection unit configured to detect an output current of the inverterunit and generate a current signal, and a control unit configured togenerate a control signal for controlling the inverter unit. The controlunit includes an impedance estimation unit configured to inject adisturbance signal into the load and derive an estimated value of animpedance of the load based on the voltage signal from the load intowhich the disturbance signal is injected, an impedance compensator unitin which a control parameter is set based on the estimated value of theimpedance, and that is configured to correct the current signal inaccordance with the control parameter, a command value unit configuredto output a command value indicating a control target value, and acontrol compensator unit configured to generate the control signal,based on the command value from the command value unit and the currentsignal from the impedance compensator unit.

According to the present invention, an estimated value of the impedanceof a load is derived, and a control parameter is set based on theestimated value. Thus, impedance compensation adapted to thecharacteristics of the load can be realized, and favorable control ofthe load adapted to the characteristics of the load can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an exemplary application of a powerconverter according to the present invention.

FIG. 2 is a diagram showing an exemplary hardware configuration of asystem interconnection inverter (example of the power converter)according to an embodiment.

FIG. 3 is a diagram showing an exemplary configuration of an impedanceestimation unit in the system interconnection inverter.

FIG. 4 is a diagram showing the sequence of a control parameter settingoperation in the system interconnection inverter.

FIG. 5 is a diagram showing an example of a waveform of a disturbancesignal that is output by the system interconnection inverter.

FIG. 6 is a diagram showing an example of the change in a disturbancewaveform amplification factor derived from a response signal to adisturbance signal relative to frequency.

FIG. 7 is a diagram for illustrating a method for calculating systemimpedance (LineLz) from a measured resonance frequency (fc).

FIG. 8 is a diagram showing the relationship between measured resonancefrequency (fc) and system impedance (LineLz).

FIGS. 9A and 9B are diagrams showing results of simulating impedanceestimation.

FIG. 10 is a diagram showing an exemplary configuration in which a notchfilter is applied to an impedance suppression compensator unit in asystem interconnection inverter according to a first variation.

FIG. 11 is a Bode diagram in cases where a notch filter is and is notprovided in the system interconnection inverter.

FIG. 12 is a diagram showing an exemplary configuration in which a phaseadvance compensator is applied to an impedance suppression compensatorunit in a system interconnection inverter according to a secondvariation.

FIG. 13 is a diagram showing an exemplary configuration in which anobserver is applied to an impedance suppression compensator unit in asystem interconnection inverter according to a third variation.

FIG. 14 is a diagram showing an exemplary hardware configuration of animpedance estimation unit in a system interconnection inverter accordingto a fourth variation.

FIG. 15 is a diagram showing an exemplary hardware configuration of asystem interconnection inverter according to a fifth variation.

DETAILED DESCRIPTION

Hereinafter, an embodiment according to one aspect of the presentinvention will be described based on the accompanying drawings.

1 Exemplary Application

An example of a situation in which a power converter of the presentinvention is applied will be described using FIG. 1. FIG. 1 is a diagramschematically showing an example in which the power converter of thepresent invention is applied to a system interconnection inverter 100.The system interconnection inverter 100 is connected to a poletransformer 500 via wiring 520. The system interconnection inverter 100converts DC power generated by a solar cell 300 into AC power andsupplies the AC power to the system. The system interconnection inverter100 estimates the system impedance (particularly the inductor component(LineLz)), which is the impedance of the wiring 520 from the systeminterconnection inverter 100 to the pole transformer 500, and setscontrol parameters such that the control system will be stable, based onthe estimated system impedance. Here, the control parameters are settingvalues for controlling the operating characteristics of the systeminterconnection inverter 100.

Specifically, the system interconnection inverter 100 injectsdisturbance (disturbance signal) into the system 500, receives aresponse to the disturbance from the system 500, estimates the systemimpedance (LineLz) based on the response, and sets control parametersrelating to impedance compensation such that the control system will bestable, based on the estimated system impedance. Appropriate impedancecompensation that depends on the conditions of the location in which thesystem interconnection inverter 100 is installed can thereby berealized, enabling stable control. Also, since the control parametersare set using the system impedance estimated (measured) in theinstallation environment of the system interconnection inverter 100, itis not necessary to design using large components with a margin builtin, and miniaturization of components and cost reduction can berealized.

In the following description, a system interconnection inverter isdescribed as an example of the power converter according to the presentinvention, but the power converter according to the present invention isnot limited to a system interconnection inverter, and can also beapplied to an inverter circuit that is used in each of anuninterruptible power supply (UPS), an independent inverter, a servocontroller, and a motor controller. That is, the power converteraccording to the present invention can be widely applied to variousdevices that convert DC power into AC power and supply the AC power to aload (control target). For example, the power converter of the presentinvention, when applied to an inverter circuit of a motor controllerthat controls a motor (load), may estimate the impedance of the motor,and set control parameters relating to impedance compensation, based onthe estimated impedance value.

2 Exemplary Configuration

2.1 Hardware Configuration

2.1.1 System Interconnection Inverter

An example of the hardware configuration of the system interconnectioninverter 100, which is one embodiment of the power converter accordingto the present invention, will be described using FIG. 2. FIG. 2 is adiagram schematically showing an example of the hardware configurationof the system interconnection inverter 100. The system interconnectioninverter 100 is a device that converts DC power from a DC power supply 1into AC power and outputs the AC power to a system 6. Here, the DC powersupply 1 is a power supply that outputs DC voltage, and is, for example,a solar cell or a fuel cell.

In the example in FIG. 2, the system interconnection inverter 100 isprovided with a capacitor 2, an inverter circuit 3, an LC filter circuit4, a current detection unit 7, a voltage detection unit 8, a PWMwaveform generation unit 9, and a control unit 10.

The capacitor 2 smoothes the DC voltage from the DC power supply 1. Theinverter circuit 3 is a circuit that converts DC voltage input via thecapacitor 2 into AC voltage having a desired frequency and voltage. Theinverter circuit 3 includes a full-bridge circuit of switching elements.The LC filter circuit 4 includes an inductor and a capacitor. The LCfilter circuit 4 has a function of shaping a pulse waveform that isoutput by the inverter circuit 3 into a sine waveform. The systeminterconnection inverter 100 is interconnected to the system 6 via theLC filter circuit 4, and outputs power to the system 6.

In FIG. 2, the impedance of the lead routing between the systeminterconnection inverter 100 and the system 6 (specifically, poletransformer) is shown as a system impedance 5. The system impedance 5includes an inductor component and a resistance component. Note that, inthe present embodiment, as components of the imaginary part of thesystem impedance 5, a capacitance component is considered small enoughto disregard and only the inductor component is taken intoconsideration, but the capacitance component may be included in theimaginary part of the system impedance.

The voltage detection unit 8 detects the voltage of the system 6, andoutputs a voltage signal indicating the value of the detected voltage.The current detection unit 7 detects the output current of the systeminterconnection inverter 100, and outputs a current signal indicatingthe value of the output current.

The PWM waveform generation unit 9 generates a PWM (Pulse WidthModulation) signal for driving each switching element of the invertercircuit 3, based on a control signal from the control unit 10, andoutputs the PWM signal to the inverter circuit 3.

The inverter circuit 3 converts the DC voltage smoothed by the capacitor2 into an AC voltage, and outputs the AC voltage to the system 6 via theLC filter circuit 4.

The control unit 10 generates a control signal for controlling theinverter circuit 3, based on the current signal from the currentdetection unit 7 and the voltage signal from the voltage detection unit8, such that the output current of the system interconnection inverter100 will take a control target value. The control unit 10 is providedwith a control compensator unit 11, a command value generation unit 12,an impedance suppression compensator unit 13, an impedance estimationunit 14, a changeover switch 15, a subtractor 31, and an adder 32. Thecontrol unit 10 includes a CPU (Central Processing Unit), a RAM (RandomAccess Memory) and a ROM (Read Only Memory), and controls theconstituent elements according to information processing. Programs thatare executed by the control unit 10 may be provided via a network or viaa recording medium such as an optical disk or a memory card. Also, thecontrol unit 10 may be a semiconductor device (FPGA, ASIC, etc.)designed exclusively in order to realize a predetermined functionality.

The command value generation unit 12 generates a command value, which isa control target value (target current value) of the output of thesystem interconnection inverter 100, and outputs the command value tothe control compensator unit 11.

The control compensator unit 11 performs PID (Proportional IntegralDifferential) control in accordance with the command value from thecommand value generation unit 12 and the output from the impedancesuppression compensator unit 13, and generates a control signal fordriving the inverter circuit 3.

The impedance estimation unit 14 estimates (measures) the systemimpedance. That is, the impedance estimation unit 14 derives, as anestimated value of the system impedance, the value of the imaginary part(LineLz) attributable to the inductor component of the system impedance.Note that, in the following description, the imaginary part of thesystem impedance 5 will be referred to simply as “the system impedance”,for convenience of description.

Specifically, the impedance estimation unit 14 generates a disturbancesignal of a sine wave, and injects the disturbance signal into thesystem 6. The impedance estimation unit 14 then receives a response(voltage signal) from the system 6 into which the disturbance signal isinjected, and derives an estimated value (LineLz) of the systemimpedance based on the response. The configuration of the impedanceestimation unit 14 will be described in detail later. The estimatedvalue of the system impedance derived by the impedance estimation unit14 is sent to the impedance suppression compensator unit 13.

The changeover switch 15 is a switch for switching between injecting andnot injecting the disturbance signal that is output by the impedanceestimation unit 14 into the system 6. When the changeover switch 15 isON, the disturbance signal is injected into the system 6.

The adder 32 adds the disturbance signal from the impedance estimationunit 14 to the command value from the command value generation unit 12.

The impedance suppression compensator unit 13 is means for compensatingfor the effect of the system impedance. The control parameters of theimpedance suppression compensator unit 13 are set based on the estimatedvalue of the system impedance. The impedance suppression compensatorunit 13 receives the current signal from the current detection unit 7.During the operation of deriving the estimated value of the systemimpedance, the impedance suppression compensator unit 13 directlyoutputs the current signal from the current detection unit 7 (i.e., thecurrent signal from the current detection unit 7 is output after beingamplified by a gain 1). On the other hand, at the time of normaloperation of the system interconnection inverter 100, the impedancesuppression compensator unit 13 corrects the current signal from thecurrent detection unit 7 in accordance with the control parameters. Thecontrol parameters are parameters for controlling the operatingcharacteristics of the impedance suppression compensator unit 13, andare, for example, setting values for controlling the gain and/or phaseof the output of the impedance suppression compensator unit 13.

The subtractor 31 calculates the difference between the output of theadder 32 and the output of the impedance suppression compensator unit13.

The control compensator unit 11 generates a control signal for PWMdriving each switching element of the inverter circuit 3, based on theoutput from the subtractor 31, such that the output current of theinverter circuit 3 will take a target value.

2.1.2 Impedance Estimation Unit

FIG. 3 is a diagram schematically showing an example of theconfiguration of the impedance estimation unit 14 in the systeminterconnection inverter 100. The impedance estimation unit 14 isprovided with a disturbance frequency generation unit 16, a disturbancegeneration unit 17, a storage unit 18, a resonance frequency estimationunit 19, and an impedance operation unit 20.

The disturbance frequency generation unit 16 sets the frequency of thedisturbance signal, and outputs a signal indicating the frequency. Thedisturbance frequency generation unit 16 changes the frequency of thedisturbance signal within a predetermined range (f_min to f_max). Thedisturbance generation unit 17 generates a disturbance signal of thefrequency instructed by the disturbance frequency generation unit 16,based on the output signal from the disturbance frequency generationunit 16. Here, a disturbance signal (Pd) is a sine wave with very lowpower, and is represented by the following equation.Pd=A sin(2πft)f_min≤f≤f_maxHere, A is the amplitude of the disturbance signal, t is the timeperiod, f is the frequency of the disturbance signal, f_min is theminimum value of the frequency of the disturbance signal, and f_max isthe maximum value of the frequency of the disturbance signal.

The storage unit 18 stores the value of the response signal to thedisturbance signal and the frequency of the disturbance signal inassociation with each other. The storage unit 18 is a RAM, for example.The resonance frequency estimation unit 19 derives a resonance frequencyfc of a response signal using information stored in the storage unit 18.The impedance operation unit 20 derives and outputs the imaginary part(LineLz) of the system impedance based on the resonance frequency fc.

3 Exemplary Operations

Operations of the system interconnection inverter 100 that isconstituted as described above will be described. The systeminterconnection inverter 100 performs operations for setting controlparameters when connected to the system 6. Specifically, the systeminterconnection inverter 100 estimates the system impedance, and setsthe control parameters of the impedance suppression compensator unit 13based on the value of the estimated system impedance. Thereafter, thesystem interconnection inverter 100 performs operations for normaloperation that involve converting direct current from a DC power supplyinto alternating current and outputting the alternating current to thesystem 6. Hereinafter, the operations for normal operation and theoperations for setting control parameters by the system interconnectioninverter 100 will respectively be described.

3.1 Normal Operation

First, operations for normal operation by the system interconnectioninverter 100 will be described. Operations for normal operation areoperations for realizing the original function of the systeminterconnection inverter 100 that involves converting the DC power ofthe DC power supply 1 into AC power and supplying the AC power to thesystem 6. Operations for normal operation are performed after thecontrol parameters have been set.

The system interconnection inverter 100 receives the DC voltage from theDC power supply 1. The input DC voltage is smoothed by the capacitor 2,and output to the inverter circuit 3. The inverter circuit 3 convertsthe DC power into AC power.

The LC filter circuit 4 smoothes the output of the inverter circuit 3,and outputs the smoothed output to the system 6. The current detectionunit 7 detects the output current of the inverter circuit 3, and outputsa current signal indicating the detected value. The voltage detectionunit 8 detects the output voltage of the inverter circuit 3, and outputsa voltage signal indicating the detected value. The control unit 50generates a control signal for driving the inverter circuit 3, using thecurrent signal from the current detection unit 7 and the voltage signalfrom the voltage detection unit 8.

In the control unit 10, at the time of operations for normal operation,the changeover switch 15 is controlled to be OFF, and the impedanceestimation unit 14 has stopped its operation. A disturbance signal isthereby not injected into the system 6 at the time of operations fornormal operation.

The command value generation unit 12 receives the voltage signal fromthe voltage detection unit 8, and generates a command value (currentcommand value), which is the control target value. Specifically, thecommand value generation unit 12 receives the voltage signal from thevoltage detection unit 8, generates a sine wave based on the zero crosstiming of the voltage signal, and generates a command value inaccordance with the sine wave.

The subtractor 31 calculates the difference (current difference) betweenthe command value generated by the command value generation unit 12 andthe current signal from the impedance suppression compensator unit 13.The control compensator unit 11 generates a control signal for drivingthe inverter circuit 3, based on that difference.

At this time, the impedance suppression compensator unit 13 corrects andoutputs the current signal from the current detection unit 7.Beforehand, the control parameters of the impedance suppressioncompensator unit 13 are set based on the estimated value of the systemimpedance. Thus, a current signal (feedback signal) that compensates forthe effect of the system impedance is output from the impedancesuppression compensator unit 13.

The PWM waveform generation unit 9 generates a drive signal (PWM signal)for driving each switching element of the inverter circuit 3, inaccordance with the control signal from the control unit 10, and outputsthe drive signal to the inverter circuit 3. In the inverter circuit 3,each switching element is thereby driven, and desired AC power isgenerated and output.

3.2 Setting of Control Parameters Based on System Impedance

Next, the operations for setting the control parameters in the systeminterconnection inverter 100 will be described. The operations forsetting of the control parameters are performed at the time ofinstalling the system interconnection inverter 100, for example. In theoperations for setting the control parameters, the estimated value ofthe system impedance (LineLz) is calculated and the control parametersof the impedance suppression compensator unit 13 are set based on theestimated value that is calculated.

FIG. 4 is a diagram showing the operation sequence relating to theoperations for setting the control parameters of the systeminterconnection inverter 100. Hereinafter, the operations for settingthe control parameters of the system interconnection inverter 100 willbe described using FIG. 4.

First, the inverter circuit 3 of the system interconnection inverter 100starts output of the voltage that is synchronized with system power(S1). The command value generation unit 12 of the control unit 10 thusgenerates and outputs a command value indicating the control targetvalue.

Thereafter, the control unit 10 controls the changeover switch 15 to beON, in order to calculate an estimated value of the system impedance(S2). Injection of a disturbance signal for estimating the systemimpedance into the system 6 thereby becomes possible.

In the impedance estimation unit 14, the disturbance frequencygeneration unit 16 sets the frequency of the disturbance signal to aninitial value f_min (S3). The initial value f min is the minimum valueof the frequency of the disturbance signal. The disturbance generationunit 17 generates and outputs a command value (hereinafter, “disturbancecommand value”) of the disturbance signal having the frequency (f_min)set by the disturbance frequency generation unit 16 (S4). At this time,since the changeover switch 15 is ON, the disturbance command value fromthe impedance estimation unit 14 is added to the command value from thecommand value generation unit 12 by the adder 32 (S4).

In the subtractor 31, the difference between the command value to whichthe disturbance command value was added and the current signal from theimpedance suppression compensator unit 13 is calculated. At this time(during calculation of the estimated value of the system impedance), theimpedance suppression compensator unit 13 outputs the output signal fromthe current detection unit 7 directly, that is, after multiplying theoutput signal by the gain 1.

The control compensator unit 11 generates a control signal of theinverter circuit 3 based on the difference calculated by the subtractor31, and transmits the control signal to the PWM waveform generation unit9. The PWM waveform generation unit 9 drives the inverter circuit 3 inaccordance with the control signal, and generates AC power that isoutput to the system 6. As a result, with respect to the system 6, adisturbance signal is injected into the system 6 in addition to the ACpower obtained through conversion based on the DC power from the DCpower supply 1.

FIG. 5 is a diagram showing an example of a waveform of the disturbancesignal that is injected into the system 6. FIG. 5(B) is an enlarged viewshowing the waveform near the zero crossing in the waveform shown inFIG. 5(A). As shown in FIG. 5, the disturbance signal Pd (high frequencysine wave) is superimposed on a waveform P (low frequency sine wave) ofthe original output power of the system interconnection inverter 100.

Returning to FIG. 4, the impedance estimation unit 14 of the controlunit 10 receives the voltage signal from the voltage detection unit 8 asa response to the disturbance signal. The impedance estimation unit 14measures an amplification factor G of the disturbance waveform from thereceived response, and saves the amplification factor G to the storageunit 18 in association with the frequency f of the injected disturbancesignal (S5).

The control unit 10 repeats the above processing, while changing thefrequency of the disturbance signal that is injected at a predeterminedinterval (fstep) (S11), until the disturbance frequency reaches themaximum value (f_max) (S4 to S6, S11). By adopting this configuration,the disturbance signal is injected into the system 6 while changing thefrequency of the disturbance signal stepwise (every fstep) in apredetermined range (f_min to f_max), the response at each frequency ismeasured, and the amplification factor G of the disturbance waveform isderived.

When measurement of the response to the disturbance signal is completedfor the frequencies in the predetermined range (f_min to f_max) (YES atS6), the disturbance generation unit 17 stops output of the disturbancecommand value (S7). The resonance frequency estimation unit 19 derivesthe resonance frequency fc using the data stored in the storage unit 18(S7). FIG. 6 is a diagram showing an example of the change in thedisturbance waveform amplification factor G derived from the response tothe disturbance signal relative to frequency. The resonance frequencyestimation unit 19 derives the frequency when the disturbance waveformamplification factor G is at a maximum as the resonance frequency fc.

Thereafter, the changeover switch 15 is set to OFF (S8). The impedanceoperation unit 20 calculates an estimated value (LineLz) of the systemimpedance from the resonance frequency fc (S9). The method forcalculating the estimated value (LineLz) of the system impedance will bedescribed in detail later.

The impedance suppression compensator unit 13 sets the controlparameters based on the estimated value (LineLz) of the system impedancethat is calculated (S10). The configuration and operations of theimpedance suppression compensator unit 13 will be described in detaillater.

As described above, the system interconnection inverter 100 of thepresent embodiment injects a disturbance signal into the system 6,measures the response to the injected disturbance signal, and measuresthe system impedance (LineLz) based on the measured response. The systeminterconnection inverter 100 then sets the control parameters of theimpedance suppression compensator unit 13 based on the measured systemimpedance (LineLz).

In this way, the system impedance (LineLz) is actually measured and thecontrol parameters are set based on the measured system impedance, thusenabling favorable control adapted to the installation conditions(system impedance) of the system interconnection inverter 100.

3.2.1 Calculation of Estimated Value of System Impedance

Hereinafter, a method for calculating the system impedance (LineLz) fromthe resonance frequency fc will be described, with reference to FIG. 7.

FIG. 7 is a diagram showing the inverter circuit 3 of the systeminterconnection inverter 100 of the present embodiment and an equivalentcircuit of the system 6. The circuit equation for the equivalent circuitof FIG. 7 is as shown in the following equation (1).

$\begin{matrix}{{{Vout}(s)} = \frac{\left( {\frac{{Vinv}(s)}{ACLs} + \frac{{Vs}(s)}{LineLzs}} \right) \times \frac{1}{ACCs}}{1 + {\left( {\frac{1}{ACLs} + \frac{1}{LineLzs}} \right) \times \frac{1}{ACCs}}}} & (1)\end{matrix}$Here, Vinv is the output of the inverter circuit 3, Vout is the outputof the system interconnection inverter 100, ACL is the inductorcomponent of the LC filter circuit 4, ACC is the capacitance componentof the LC filter circuit 4, and LineLz is the value of the imaginarypart (amount contributed by the inductor) of the system impedance.

In equation (1), when the output Vout(s) of the system interconnectioninverter 100 is at a maximum, the denominator is at a minimum, that is,the denominator becomes even closer to 0 without limit. Therefore, whenequation (1) is solved for LineLz where the denominator is 0, thefollowing equation (2) is obtained.

$\begin{matrix}{{LineLz} = \frac{ACL}{{{ACL} \times {ACC} \times \left( {2\pi\; f} \right)^{2}} - 1}} & (2)\end{matrix}$Here, s=j2πf (where j is the imaginary unit and f is the frequency).

ACL and ACC are component constants and are known values. The outputVout(s) of the system interconnection inverter 100 is at a maximum whenthe frequency f is the resonance frequency fc. Therefore, the systemimpedance LineLz can be derived, by substituting the value of theresonance frequency fc for f in equation (2).

The values of ACL and ACC are determined at the time of hardware design.FIG. 8 is a diagram showing the relationship between the resonancefrequency fc and the system impedance LineLz, which is based on theabove equation (2), when ACL=0.00036H and ACC=0.000015F, for example.The designer appropriately sets the range of the system impedance LineLzas a specification. If the range of values of the system impedanceLineLz that are desirably measured is known in advance, the range overwhich the frequency of the response signal can change, that is, theminimum f_min and maximum f_max of the frequency, can be determined fromthe relationship shown in FIG. 8. For example, in the case whereACL=0.00036H and ACC=0.000015F, and the range of values of the systemimpedance LineLz that are desirably derived is 0.1 mH to 8 mH, themaximum f_max and minimum f_min of the frequency will, from therelationship in equation (2), respectively be 4645.176 Hz and 2214.019Hz.

FIGS. 9A and 9B are diagrams for illustrating the accuracy of theestimated value of the system impedance derived by the above method.FIG. 9A is a diagram that numerically contrasts error between the truevalue and the estimated value for three different system impedances.FIG. 9B is a diagram representing the values shown in FIG. 9A with agraph. It is evident from these diagrams that the estimated value of thesystem impedance is accurately obtained by the method shown in thepresent embodiment.

3.3 Operation and Effect

As described above, the system interconnection inverter 100 (example ofthe power converter) of the present embodiment is a device that convertsDC power from the DC power supply 1 into AC power and outputs the ACpower to the system 6 (example of the load). The system interconnectioninverter 100 is provided with the inverter circuit 3 (example of theinverter unit) that converts DC power from the DC power supply 1 into ACpower, the voltage detection unit 8 that detects the voltage of thesystem 6 and generates a voltage signal, the current detection unit 7that detects the output current of the inverter circuit 3 and generatesa current signal, and the control unit 10 that generates a controlsignal for controlling the inverter circuit 3.

The control unit 10 includes the impedance estimation unit 14 thatinjects a disturbance signal into the system 6 and derives an estimatedvalue of the system impedance (example of the impedance of the load)based on the voltage signal from the system 6 into which the disturbancesignal is injected, the impedance suppression compensator unit 13(example of the impedance compensator unit) in which control parametersare set based on the estimated value of the system impedance, and thatcorrects the current signal in accordance with the control parameters,the command value generation unit 12 (example of the command value unit)that outputs a command value indicating a control target value, and thecontrol compensator unit 11 that generates a control signal based on thecommand value from the command value generation unit 12 and the currentsignal from the impedance suppression compensator unit 13.

As a result of adopting the above configuration, the systeminterconnection inverter 100 injects a disturbance signal into thesystem 6, derives an estimated value (LineLz) of the system impedancebased on the response to the disturbance signal, and sets the controlparameters based on the estimated value. Impedance compensation canthereby be realized based on the system impedance in the actual useenvironment of the system interconnection inverter 100, and favorablepower control adapted to the system impedance can be realized. As aresult, it becomes unnecessary to build a margin into the design withconsideration for the maximum value of the impedance that is envisagedin advance as was heretofore required, and the components of the systeminterconnection inverter 100 can be designed to be physically small,enabling increases in the size and cost of the system interconnectioninverter 100 to be suppressed.

4 Variations

4.1 First Variation

In the first variation, a specific example of the configuration of theimpedance suppression compensator unit 13 in the control unit 10 will bedescribed. In the first variation, a notch filter is applied to theimpedance suppression compensator unit 13, in order to suppress anincrease in gain due to the resonance point of the system impedance(LineLz) and the impedances (ACL, ACC) of the LC filter circuit 4.

FIG. 10 shows an exemplary configuration of the system interconnectioninverter 100 to which a notch filter 13 b is applied. Characteristics(transfer function) of the notch filter 13 b are shown below using acenter frequency fs.

$\begin{matrix}\frac{s^{2} + \left( {2\pi\; f_{s}} \right)^{2}}{s^{2} + {2\pi\; f_{s}\xi\; s} + \left( {2\pi\; f_{s}} \right)^{2}} & (3)\end{matrix}$

On the other hand, the resonance point fs of the current control systemis derived with the following equation. Here, ACL is the inductorcomponent of the LC filter circuit 4, and ACC is the capacitancecomponent of the LC filter circuit 4.

$\begin{matrix}{{fs} = \frac{\sqrt{\frac{\frac{1}{ACL} + \frac{1}{LineLz}}{ACC}}}{2\pi}} & (4)\end{matrix}$

The control unit 10 calculates the value of the resonance point fs inaccordance with the estimated value of the system impedance LineLzreceived from the impedance estimation unit 14 and equation (4), andsets the calculated value of the resonance point fs as the centerfrequency fs (refer to equation (3)) in the notch filter 13 b. In thisway, the gain at the resonance point is suppressed, by setting thecenter frequency fs of the notch filter 13 b as a control parameter,based on the estimated value of the system impedance LineLz.

FIG. 11 is a Bode diagram of the system interconnection inverter 100 incases where the notch filter 13 b is and is not provided. As shown inFIG. 11, in the case where the notch filter 13 b is not provided, thegain (B point) at the frequency at which the phase shifts 180 degreesexceeds 0 dB, as shown by the two-dot chain line. The control systemthus becomes unstable. On the other hand, in the case where the notchfilter 13 b is installed in the impedance suppression compensator unit13, the gain (A point) at the frequency at which the phase shifts 180degrees is suppressed to less than 0 dB, as shown by the solid line inFIG. 11. The control system can thus be stabilized.

4.2 Second Variation

In the second variation, another specific exemplary configuration of theimpedance suppression compensator unit 13 in the control unit 10 will bedescribed. In the second variation, a phase advance compensator isapplied to the impedance suppression compensator unit 13, in order tosuppress phase delay due to the resonance point of the system impedance(LineLz) and the impedances (ACL, ACC) of the LC filter circuit 4.

FIG. 12 shows an exemplary configuration of the system interconnectioninverter 100 to which a phase advance compensator 13 c is applied. Thecharacteristics of the phase advance compensator 13 c are shown by thefollowing equation.

$\begin{matrix}\frac{1 + {sf}_{1}}{1 + {sf}_{2}} & (5)\end{matrix}$

The control unit 10 sets the characteristics of the phase advancecompensator 13 c, by calculating the resonance point fs in accordancewith the estimated value of the system impedance LineLz received fromthe impedance estimation unit 14 and equation (4), and setting thefrequencies f1 and f2 shown in equation (5), based on the value of thecalculated resonance point fs. In this way, phase delay due to theresonance point is suppressed by setting the characteristics of thephase advance compensator 13 c based on the estimated value of thesystem impedance LineLz.

Specifically, in the phase advance compensator 13 c, the break frequencyis set in a frequency lower than the resonance point fs to advance thephase in the resonance point fs, and the relationship where the phase inthe resonance point fs is less than 180 degrees is maintained. That is,in equation (5), the phase can be advanced in bands from fs−f1 to fs+f2,by setting f1 and f2 such that f1<fs and f2>fs are satisfied, based onthe resonance point fs derived from the estimated value of the systemimpedance LineLz. The control system can thereby be stabilized. In thisway, in the second variation, the control parameters (f1, f2) forcontrolling the amount of phase advance of the phase advance compensator13 c are set based on the estimated value of the system impedanceLineLz.

4.3 Third Variation

In the third variation, yet another specific exemplary configuration ofthe impedance suppression compensator unit 13 in the control unit 10will be described. In the third variation, an observer 13 d is set asthe impedance suppression compensator unit 13, and stability is securedthrough pole assignment by state feedback.

FIG. 13 shows an exemplary configuration of the system interconnectioninverter 100 to which the observer 13 d is applied as the impedancesuppression compensator unit 13. The impedance estimation unit 14 in thethird variation also calculates an estimated value (Rz) of the real partof the system impedance. Specifically, the impedance estimation unit 14calculates a value Z of the overall system impedance including both thereal part and the imaginary part from the voltage signal and the currentsignal. The impedance estimation unit 14 then derives the estimatedvalue (Rz) of the real part of the system impedance from the value (Z)of the overall system impedance and the estimated value (LineLz) of theimaginary part of the system impedance, based on the followingrelational equation.Z ²=√{square root over (Rz ²+LineLz ²)}  (6)

The observer 13 d is built to behave in the same manner as a circuitmodel of the system interconnection inverter 100. The observer 13 dreflects the estimation result by the impedance estimation unit 14 inthe circuit model. That is, the observer 13 d substitutes the estimatedvalue (Rz) of the real part of the system impedance as the resistancecomponent and the estimated value (LineLz) of the imaginary part of thesystem impedance as the inductance component in the circuit model,performs simulation, and outputs the simulation result of the outputcurrent value of the inverter circuit 3. The observer 13 d derives anend-to-end voltage of the system impedance that has not actually beenmeasured and the estimated value of the current, and builds statefeedback based on these estimated values. The observer 13 d sets thestate feedback gain, and secures stability through pole assignment. Inthis way, in the third variation, circuit constants of the circuit modelof the observer 13 d are set as control parameters, based on theestimated value of the system impedance LineLz. Note that, with respectto the observer 13 d, a configuration may be adopted in which only theestimated value (LineLz) of the imaginary part of the system impedanceis substituted.

4.4 Fourth Variation

In the above embodiment, the amplitude of the disturbance signal isgiven as being constant (fixed) during injection of the disturbancesignal. In this case, depending on the Q value of the resonance of thesystem 6 serving as the load, the injected disturbance signal may begreatly amplified, and the disturbance signal may excessively affect thesystem 6. In the fourth variation, a configuration for reducing theeffect on the system 6 due to such amplification of the disturbancesignal will be described.

The system interconnection inverter 100 of the fourth variation differsfrom above embodiment in the configuration of the impedance estimationunit. FIG. 14 is a diagram schematically showing an exemplary hardwareconfiguration of an impedance estimation unit 14 b in the systeminterconnection inverter 100 of the fourth variation. The impedanceestimation unit 14 b of the fourth variation has a function ofcontrolling the amplitude of the disturbance signal that is injected.Thus, as shown in FIG. 14, the impedance estimation unit 14 b is furtherprovided with a band pass filter 22, a peak value calculation unit 23, adisturbance amplitude reference value generation unit 24, a disturbanceamplitude compensator 21, a subtractor 33 and a multiplier 34, inaddition to the configuration of the impedance estimation unit 14 shownin FIG. 3.

The band pass filter 22 passes only a signal of the same frequencycomponent as the disturbance signal in the voltage signal from thevoltage detection unit 8. The peak value calculation unit 23 receivesthe output from the band pass filter 22, and calculates the peak valueof the voltage of the system.

The disturbance amplitude reference value generation unit 24 sets thereference value of the amplitude of the disturbance signal which is asine wave. For example, in the case where it is assumed that the maximumvalue of the peak value of the output voltage is “1”, “1” is set as areference value of the amplitude of the disturbance signal.

The subtractor 33 computes the difference between the reference valueset by the disturbance amplitude reference value generation unit 24 andthe peak value derived by the peak value calculation unit 23. Thedisturbance amplitude compensator 21 generates gain for controlling theamplitude of the disturbance signal, based on the difference computed bythe subtractor 33.

The multiplier 34 multiplies the command value output by the disturbancegeneration unit 17 by the gain generated by the disturbance amplitudecompensator 21, and outputs the resultant value as a final disturbancecommand value. At this time, the gain that is output by the disturbanceamplitude compensator 21 is stored in the storage unit 18 in associationwith the frequency of the disturbance signal, for every frequency thatis changed.

As a result of a configuration such as described above, the amplitude ofthe disturbance signal that is injected into the system 6 is controlled(adjusted) based on a fluctuation component (amplitude) caused by theinjected disturbance signal. That is, when there is a large fluctuationin the power of the system 6 caused by the disturbance signal injectedinto the system 6, control is performed such that the amplitude of thedisturbance signal decreases. The fluctuation in power due to thedisturbance signal that is injected into the system 6 can thereby besuppressed, and the effect of disturbance injection on the system 6 canbe reduced.

4.5 Fifth Variation

In the system interconnection inverter 100 shown in FIG. 2, a currentcomponent that occurs due to the injected disturbance is also includedin the current signal that is detected by the current detection unit 7,while the disturbance signal is being injected, in addition to thecurrent component that occurs due to the original command value outputby the command value generation unit 12. At this time, the controlcompensator unit 11, in the case where this current signal is used asthe feedback signal, suppresses the disturbance signal injected into thesystem, and, as a result, the correct response signal may not beobtained. In the fifth variation, a configuration of the systeminterconnection inverter 100 that solves this problem will be described.

FIG. 15 is a diagram showing an exemplary configuration of the systeminterconnection inverter 100 in the fifth variation. As shown in FIG.15, the control unit 10 in the system interconnection inverter 100 ofthe fifth variation is further provided with a notch filter 25 andchangeover switches 15 b and 15 c, in addition to the configurationshown in FIG. 2.

The notch filter 25 is a filter having characteristics such as shown inequation (3), and attenuates the signal of a predetermined band (centerfrequency fs). The current signal is input to the notch filter 25 fromthe current detection unit 7.

The changeover switch 15 b selectively connects the output of one of theimpedance suppression compensator unit 13 and the notch filter 25 to thesubtractor 31. The changeover switch 15 c selectively connects theoutput of the impedance estimation unit 14 to the input of one of theimpedance suppression compensator unit 13 and the notch filter 25.

While disturbance is being injected in order to derive an estimatedvalue of the system impedance, the control unit 10 performs control toconnect the changeover switches 15 b and 15 c to the notch filter 25side. Information indicating the frequency of the disturbance signal isthereby input from the impedance estimation unit 14 to the notch filter25 via the changeover switch 15 c.

The notch filter 25 sets the center frequency fs to the same frequencyas the frequency of the disturbance signal, in accordance with theinformation input from the impedance estimation unit 14. The notchfilter 25 thereby outputs a signal that result from removing the signalof the same frequency component as the disturbance signal from thecurrent signal output by the current detection unit 7. In this way, byusing the notch filter 25 to suppress, in the current signal, only thefrequency band of the disturbance signal that is being injected, thecontrol response can be desensitized in only the injection frequencyband. As a result, the correct response signal can be obtained for thedisturbance signal.

After calculation of the estimated value of the system impedance hasended (i.e., after the end of injection of the disturbance signal), thechangeover switches 15 b and 15 c are switched to the impedancesuppression compensator unit 13 side. At the time of normal operation ofthe system interconnection inverter 100, the current signal is therebyprocessed by the impedance suppression compensator unit 13 in whichcontrol parameters were set based on the estimated system impedancevalue, as described above. Stable control can thereby be realized.

Note that, in the case of using a notch filter 13 b such as shown inFIG. 10 as the impedance suppression compensator unit 13, the notchfilter 13 b may be operated as the notch filter 25, during the operationfor estimating the system impedance. In this case, the changeoverswitches 15 b and 15 c are not required.

The specific configurations described in the fourth and fifth variationscan be combined as appropriate with the configurations described in theabove embodiment and other variations.

The embodiment described above is merely an illustrative example of aspecific configuration of the present invention. Needless to say,various improvements through modification, substitution, deletion andthe like can be made, without departing from the scope of the presentinvention.

5 Additional Remarks

The description in the above embodiment discloses the followingconfigurations.

(A) A power converter (100) for converting DC power from a DC powersupply (1) into AC power and outputting AC power to a load (6),including:

an inverter unit (3) configured to convert DC power from the DC powersupply into AC power;

a voltage detection unit (8) configured to detect a voltage of the loadand generate a voltage signal;

a current detection unit (7) configured to detect an output current ofthe inverter unit and generate a current signal; and

a control unit (10) configured to generate a control signal forcontrolling the inverter unit,

the control unit (10) including:

an impedance estimation unit (14) configured to inject a disturbancesignal into the load, and derive an estimated value of an impedance ofthe load into which the disturbance signal is injected, based on thevoltage signal from the load;

an impedance compensator unit (13) in which a control parameter is setbased on the estimated value of the impedance, and that is configured tocorrect the current signal in accordance with the control parameter;

a command value generation unit (12) configured to output a commandvalue indicating a control target value; and

a control compensator unit (11) configured to generate a control signalbased on the command value from the command value generation unit andthe current signal from the impedance compensator unit.

As a result of this configuration, the estimated value of the impedanceof the load is derived, and a control parameter is set based on theestimated value. Impedance compensation adapted to the use environment(i.e., the impedance of the load) of the power converter can thus berealized, and favorable control adapted to the characteristics of theload can be realized.

(B) In the power converter of (A), the impedance estimation unit mayderive the imaginary part (LineLz) of the impedance of the load as theestimated value of the impedance. The imaginary part of the impedancegreatly affects control stability. Therefore, control stability can befurther improved, by deriving the imaginary part of the impedance.

(C) In the power converter of (A), the impedance compensator unit (13)may inject the disturbance signal into the load (6) while changing thefrequency within a predetermined range, measure the voltage signal forevery frequency from the load into which the disturbance signal isinjected, and derive an estimated value of the impedance based on thefrequency (fc) of the disturbance signal when a voltage signal at amaximum is received. As a result of this method, the estimated value ofthe impedance can be accuracy derived (refer to FIGS. 9A and 9B).

(D) In any of the power converters of (A) to (C), the impedancecompensator unit (13) may be a notch filter (13 b) configured toattenuate a predetermined band component, in the current signal, thatincludes a center frequency, and the center frequency of the notchfilter may be set based on the estimated value (LineLz) of theimpedance. As a result of the notch filter, an increase in gain due tothe resonance point of the system impedance (LineLz) and the impedances(ACL, ACC) of the LC filter circuit 4 can be suppressed, and the controlsystem can be stabilized.

(E) In any of the power converters of (A) to (C), the impedancecompensator unit (13) may be a phase advance compensator (13 c)configured to advance the phase of the current signal, andcharacteristics of the phase advance compensator may be set based on theestimated value of the impedance. As a result of this configuration,phase delay due to the resonance point of the system impedance (LineLz)and the impedances (ACL, ACC) of the LC filter circuit 4 can besuppressed, and the control system can be stabilized.

(F) In any of the power converters of (A) to (C), the impedancecompensator unit (13) may be an observer (13 d) configured to simulate acircuit model of the power converter, and the value of the impedance inthe circuit model may be set based on the estimated value (LineLz) ofthe impedance. As a result of this configuration, stability can besecured through pole assignment by state feedback.

(G) In any of the power converters of (A) to (F), the impedanceestimation unit (14 b) may be provided with a disturbance amplitudecompensator (21) configured to control the amplitude of the disturbancesignal that is injected into the load (6), such that the amplitude ofthe signal of the same frequency component in the voltage signal as thedisturbance signal is constant (refer to FIG. 14). As a result of thisconfiguration, the effect of amplification of the disturbance signal onthe load (6) can be reduced.

(H) In any of the power converters of (A) to (F), the control unit (10)may be further provided with a filter (25) configured to remove thesignal of the same frequency component in the current signal as thedisturbance signal, at the time of injecting the disturbance signal intothe load (refer to FIG. 15). A current signal serving as a feedbacksignal can thereby be accurately obtained, at the time of injecting thedisturbance signal.

(I) In any of the power converters of (A) to (F), the control unit (10)is further provided with a changeover unit (15) configured to switchbetween injecting and not injecting the disturbance signal from theimpedance estimation unit (14) into the load (6).

The invention claimed is:
 1. A power converter for converting DC powerfrom a DC power supply into AC power and outputting the AC power to aload, comprising: an inverter unit configured to convert DC power fromthe DC power supply into AC power; a voltage detection unit configuredto detect a voltage of the load, and generate a voltage signal; acurrent detection unit configured to detect an output current of theinverter unit, and generate a current signal; and a control unitconfigured to generate a control signal for controlling the inverterunit, the control unit comprising a processor configured to performoperations comprising operation as: an impedance estimation unitconfigured to inject a disturbance signal into the load, and derive anestimated value of an impedance of the load based on the voltage signalfrom the load into which the disturbance signal is injected; animpedance compensator unit in which a control parameter is set based onthe estimated value of the impedance, and that is configured to correctthe current signal in accordance with the control parameter; a commandvalue unit configured to output a command value indicating a controltarget value; and a control compensator unit configured to generate thecontrol signal, based on the command value from the command value unitand the current signal from the impedance compensator unit, wherein theprocessor is configured such that operation as the impedance compensatorunit comprises operation as the impedance compensator unit that isconfigured to inject the disturbance signal into the load while changinga frequency within a predetermined range, measure the voltage signal forevery frequency from the load into which the disturbance signal isinjected, and derive the estimated value of the impedance based on thefrequency of the disturbance signal in response to a voltage signal at amaximum being received.
 2. The power converter according to claim 1,wherein the processor is configured such that operation as the impedanceestimation unit comprises operation as the impedance estimation unitthat is configured to derive an imaginary part of the impedance of theload as the estimated value of the impedance.
 3. The power converteraccording to claim 1, wherein the processor is configured such thatoperation as the impedance compensator unit comprises operation as theimpedance compensator unit comprising a notch filter configured toattenuate a predetermined band component that includes a centerfrequency in the current signal, and the center frequency of the notchfilter is set based on the estimated value of the impedance.
 4. Thepower converter according to claim 1, wherein the processor isconfigured such that operation as the impedance compensator unitcomprises operation as the impedance compensator unit comprising a phaseadvance compensator configured to advance a phase of the current signal,and a characteristic of the phase advance compensator is set based onthe estimated value of the impedance.
 5. The power converter accordingto claim 1, wherein the processor is configured such that operation asthe impedance compensator unit comprises operation as the impedancecompensator unit that comprises an observer device that simulates acircuit model of the power converter, outputs a simulation result of anoutput current value of the inverter unit, and derives estimated valuesof a voltage across the impedance and a current, which are not actuallymeasured, and a value of the impedance in the circuit model is set basedon the estimated value of the impedance.
 6. The power converteraccording to claim 1, wherein the processor is configured such thatoperation as the impedance estimation unit comprises operation as theimpedance estimation unit comprising a disturbance amplitude compensatorconfigured to control an amplitude of the disturbance signal that isinjected into the load, such that an amplitude of a signal of afrequency component in the voltage signal, which is identical to afrequency component of the disturbance signal, is constant.
 7. The powerconverter according to claim 1, wherein the control unit furtherincludes a filter configured to remove a signal of a frequency componentin the current signal, which is identical to a frequency component ofthe disturbance signal, at a time of injecting the disturbance signalinto the load.
 8. The power converter according to claim 1, wherein theprocessor is configured to perform operations further comprisingoperation as a changeover unit configured to switch between injectingand not injecting the disturbance signal from the impedance estimationunit into the load.